View T6LE2_4714966.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

T6LE2
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6LE2
Gate Driver for TFT LCD Panels
The T6LE2 is a 300 / 263 / 256-channel output gate driver for TFT LCD panels.
T6LE2
Unit: mm User Area Pitch IN OUT
Features
* LCD drive output pins * LCD drive voltage * Data transfer method * Operating temperature * Package : Switchable 300 / 263 / 256 pins : max 43.5 V : Bidirectional shift register : -20 to 75C : COF
Please contact Toshiba or a distributor for the latest COF specification and product line-up.
COF (Chip On Film)
Application
Module for PC monitors, LCDs for TV and Module for amusement
1
2006-09-20
T6LE2
Block Diagram
DO/I DI/O CPVL/R U/D MODE1 MODE2 Input circuit unit Shift register
OE L/R
Control circuit unit
XDON
VGG Output circuit unit VEE
VDD VSS
G1
G2
G3
G298 G299 G300
2
2006-09-20
T6LE2
Pin Assignment
G300 G299 G298 327 326 325
T6LE2
(chip top view)
G3 G2 G1
30 29 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
VGG VEE VDD VSS VDD DO/I (VSS) MODE2 (VDD) OE R CPVR VSS XDON (VDD) U/D (VSS) CPVL OE L (VSS) (VDD) MODE1 (VSS) DI/O VSS VDD VEE VGG
The above diagram shows the device's pin configuration only and does not necessarily correspond to the pad layout on the chip. Please contact Toshiba or our distributors for the latest COF specification.
3
2006-09-20
T6LE2
Pin Function
Pin Name I/O Function Vertical shift clock, output enable input / output select pin These pins are used to input and output shift data. These pins are switched between input and output by setting the U/D pin as shown below. U/D DI/O DO/I H I/O L DI/O Input Output DO/I Output Input
* When set for input This pin is used to feed data into the shift registers at the first stage of the LCD driver. The data is latched into the shift registers at the rising edge of CPVL/R. * When set for output When two or more T6LE2 are cascaded, this pin outputs the data to be fed into the next stage. This data changes state synchronously with the falling edge of CPVL/R. Transfer direction select / vertical shift clock, output enable input / output select pin This pin specifies the direction in which data is transferred through the shift registers. The shift register data is shifted synchronously with the rising edge of CPV as follows: When U/D is high, data is shifted in the direction U/D = "H": G1 G2 G3 G4 *** G300 When U / D is low, the direction is reversed to give U/D = "L": G300 G299 G298 G297 *** G1 This pin is used to perform input / output settings for CPVL, CPVR, OE L, OE R. U/DL U/DR I/O U/D L Input CPVR
OE R
Output CPVL
OE L
H
CPVL
OE L
CPVR
OE R
The voltage applied to this pin must be a DC-level voltage that is either high (VDD) or low (VSS). Vertical shift clock * When set for input: This is the shift clock for the shift registers. Data is shifted through the shift registers synchronously with the rising edge of CPVL/R. * When set for output: The signal input to CPVL/R is output to CPVR/L asynchronous to other signals. These pins are switched between input and output by setting the U/D pin as below. U/D H L CPVL Input Output CPVR Output Input
CPVL CPVR
I/O
OE L OE R
I/O
Output enable pin When set for input: These signals control the data appearing at the LCD panel drive pins (G1 through G300). OE L/R doesn't synchronize with the CPVL/R. When OE L/R is low : outputs shift data and data contents. When OE L/R is high : controls the LCD panel drive output to VEE level. When set for output: The signal input to OE L/R is output to OE R/L. These pins are switched between input and output by setting the U/D pin as below. U/D H L
OE L OE R
Input Output
Output Input
4
2006-09-20
T6LE2
Pin Name I/O Function Output channels select pins This signal selects 300 / 263 / 256-pin mode for the LCD panel driver. MODE1 MODE1 MODE2 I H H L L MODE2 H L H L LCD drive output pins 300-out 263-out 256-out Non-output pins G133 to G169 (VEE level ) G129 to G172 (VEE level )
XDON
I
Display-ON input pin When XDON = low, the VGG voltage is output all output pins irrespective of the shift data and the content of input data. After, the contents of the shift registers becomes unfixed the data. XON operates asynchronously with CPV. This pin is pulled-up to the VDD. Since all LCD drive outputs output (G1 to G300) the VGG level, much current may generate them momentarily. When 263 / 256-pin mode, unapplied LCD panel drive pins fixed VEE. The voltage applied to this pin must be a DC-level voltage that is either high (VDD) or low (VSS). LCD panel drive pins These pins output the shift register data or the voltage of VGG or VEE depending on the control signals OE and XDON. Power supply for LCD drive Power supply for LCD drive Power supply for the internal logic The (VDD) is the MODE1, MODE2 and U/D pin for connection. Power supply for the internal logic The (VSS) is the MODE1, MODE2 and U/D pin for connection.
G1 to G300 VGG VEE VDD VSS
O
5
2006-09-20
T6LE2
Device Operation
Shift data transfer method
Output Mode 300-out U/D Pin H L H L 263-out H L H L Shift Data Input DI/O DO/I DI/O DO/I DI/O DO/I Output DO/I DI/O DO/I DI/O DO/I DI/O
MODE1
MODE2
Data Transfer Method G1 G2 G3 G4 *** G300 G300 G299 G298 *** G1 G1 G2 G3 G4 *** G132 G170 *** G300 G300 G299 G298 *** G170 G132 *** G1 G1 G2 G3 G4 *** G128 G173 *** G300 G300 G299 G298 *** G173 G128 *** G1 Don't use
H
H
L L
H L
256-out
The input data (DI/O or DO/I) is latched into the internal register synchronously with the rising edge of the shift clock CPV. At the same time that the data is shifted to the next register at the next rise of CPV, new vertical shift data is latched into. In the output operation, the data in the last shift register (G300 or G1) is output synchronously with the falling edge of CPV. (The output high voltage is the VDD level; the output low voltage is the VSS level.)
6
2006-09-20
T6LE2
Timing Diagram 1
DI/O (Input) 1 CPVL/R
OE L/R
(300-out mode, U/D = high level, MODE1 = high level, MODE2 = high level)
2
3
4
5
300
301
XDON G1 G2 G3 G4 G300 DO/I (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin
Timing Diagram 2
DO/I (Input)
(300-out mode, U/D = low level, MODE1 = high level, MODE2 = high level)
1 CPVL/R
OE L/R
2
3
4
5
300
301
XDON G300 G299 G298 G297 G1 DI/O (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin
high level
7
2006-09-20
T6LE2
Timing Diagram 3
DI/O (Input) 1 CPVL/R
OE L/R
(263-out mode, U/D = high level, MODE1 = high level, MODE2 = low level)
2
3
4
5
263
264
XDON G1 G2 G3 G4 G133 to G169 G300 DO/I (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin
high level
VEE
Timing Diagram 4
DI/O (Input)
(256-out mode, U/D = high level, MODE1 = low level, MODE2 = high level)
1 CPVL/R
OE L/R
2
3
4
5
256
257
XDON G1 G2 G3 G4 G129 to G172 G300 DO/I (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin
high level
VEE
8
2006-09-20
T6LE2
Absolute Maximum Ratings (VSS = 0 V)
Parameter Supply voltage (1) Supply voltage (2) Supply voltage (3) Supply voltage (4) Input voltage Storage temperature Symbol VDD VGG VEE VGG - VEE VIN Tstg Rating -0.3 to 4.0 -0.3 to 48.0 -20.0 to 0.3 -0.3 to 45.0 -0.3 to VDD + 0.3 -55 to 125 C V Unit
Recommended Operating Conditions (VSS = 0 V)
Parameter Supply voltage (1) Supply voltage (2) Supply voltage (3) Supply voltage (4) Operating temperature Operating frequency Output Load capacitance Symbol VDD VGG VEE VGG - VEE Topr fCPV CL Rating 2.3 to 3.6 10 to 35 -15 to -5 15.0 to 43.5 -20 to 75 150 (max 300 (max) C kHz pF/PIN V Unit
Electrical Characteristics DC Characteristics
Parameter Low Level Input voltage (1) High Level Low Level Input voltage (2) High Level Low Level Output voltage High Level Output resistance Low Level High Level VOH ROL ROH IIN1 IIN2 IGG IDD IEE no load (Note2) VIH2 VOL IOH = -40 A VOUT = VEE + 0.5 V VOUT = VGG - 0.5 V VIN = VDD IOL = 40 A VIH1 VIL2
(VGG - VEE = 30.0 to 43.5 V, VDD = 2.3 to 3.6 V, VSS = 0 V, Ta = -20 to 75C)
Symbol VIL1 Test circuit Test Conditions Min VSS 0.7 x VDD VSS (0.7 x VDD) VSS VDD - 0.4 -1 -1 Max 0.3 x VDD VDD (0.3 x VDD) VDD VSS + 0.4 VDD 1000 1 1 T.B.D. T.B.D. T.B.D. A Unit Relevant
V
(Note1)
V
XDON
V
DI/O DO/I
G1 to G300 (Note1) XDON VGG VDD VEE
Input leakage current Current consumption (1) Current consumption (2) Current consumption (3)
A
Note1: Input pins : DI/O, DO/I, CPVL/R, OE L/R Note2: fCPV = 50kHz, Shift data input : 60Hz, OE = low level, XDON = high level, MODE1 / MODE2 = high level
9
2006-09-20
T6LE2
AC Characteristics
VGG - VEE = 30.0 to 43.5 V, VDD = 2.3 to 3.6 V, VSS = 0 V, Ta = -20 to 75C t trIN = 100ns (Max fIN = 100ns (Max)
Parameter Clock frequency CPV pulse width (H) CPV pulse width (L) Data set-up time Data hold time OE enable time Display-ON pulse width Output delay time (1) Output delay time (2) Output delay time (3) Output delay time (4) Output delay time (5) tCPVH CPVL/R 50% 50% tCPVL 50% tsDI DI/O, DO/I (Input) 50% tpdG G1 50% tpdG G2 to G300 50% thDI 50% tpdG 50% tpdG 50% VGG VEE VGG VEE 50% 50% Symbol tCPV tCPVH tCPVL tsDI thDI twOE twON tpdDO tpdG tpdOE tpdON tdlO Test circuit CL = 300 pF CL = 30 pF CL = 300 pF CL = 300 pF CL = 300 pF CL = 30 pF Test Conditions Min 500 500 200 200 1 100 Max 150 250 800 800 10 50 s ns ns s ns Unit kHz
CPVL/R
50%
50%
G300 tpdDO DO/I, DI/O (Output) 50% tpdDO 50%
VGG VEE
twOE
OE
50% tpdOE
50% tpdOE 50% VGG VEE
G1 to G300
50%
10
2006-09-20
T6LE2
twON XDON 50% tpdON G1 to G300 50% 50% tpdON 50% VGG VEE
trIN Input OE L/R, CPVL/R 50% 50%
tfIN
80% 20% 20% tdlO
tdlO Output OE L/R, CPVL/R 50%
50%
Power Supply Sequence
Turn power on in the order VDD VEE Input signal VGG. Turn power off in th reverse order. However, if can be turned off at the same time, VGG, VDD, Input signals and VEE under the condition of VEE VSS Input signals VDD VGG. The T6LE2 has a self Power on reset function. Keep the reset period : TrG 10s
TrG VDD VSS
VGG
VEE
Instruction for operating circumstances
* Light striking a semiconductor device can generate electromotive force due to photoelectric effects. In some cases this may cause the device to malfunction. This is more likely to be affected for the devices in which the surface (back), or side of the chip is exposed. At the design phase, please make sure that devices are protected against incident light from external sources. Please take into account of incident light from external sources during actual operation and during inspection. * Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Please design and manufacture products so that there is no chance of users touching the film after assembly, or if they do that, there is no chance of them injuring themselves. When cutting out the film, please ensure that the film shavings do not cause accidents. After use, please treat the leftover film and reel spacers as industrial waste.
11
2006-09-20
T6LE2
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. * The products described in this document are subject to foreign exchange and foreign trade control laws. 021023_E
12
2006-09-20

▲Up To Search▲

Price & Availability of T6LE2

	To Download T6LE2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .